This invention relates generally to improved apparatus and methods for synchronizing signals in a data processing system.
In a data processing system, timing is typically provided by one or more system clocks which are used for clocking signals into the various logic and storage elements of the system, such as flip-flops and latches. When an input signal applied to a system element is properly synchronized with an input clock pulse, reliable operation can readily be provided, since the resulting clocked signals applied to the element will have a predictable duration and energy level.
In modern day computer systems, provision must be made for properly handling asynchronous signals as well as synchronous signals, since most clocked central processors are required to interact with other systems, subsystems or peripherals having independent clocking. The central processor typically uses a clock pulse to interrogate the input line on which an asynchronous signal is applied. Since the clock pulse and the asynchronous signal have no defined relationship, the resulting effect may be a misshapen pulse (commonly referred to as a split pulse or runt pulse) which can produce unreliable results.
A well known solution to the above problem is to apply the clock pulse and the asynchronous signal to a synchronizing element, such as a flip-flop or latch. The assumption is then made that, even if the clock pulse and asynchronous signal have little overlap, the flip-flop or latch will nevertheless arrive at a stable state within some known minimum time after the clock pulse is applied, at which time the output of the synchronizing element may then be used as a properly synchronized logical pulse.
The assumption that the synchronizer element will always provide a stable output after some known minimum period of time has been found to be unreliable because, for certain pulse energy levels, a metastable state is produced which remains for an indeterminate period of time. As a result, it has been found necessary in the design of computer systems to allow a significantly greater waiting time before using the output of the synchronizing element in order to obtain an acceptable error rate. This problem has been considered, for example, in the following articles: T. J. Chaney, et al., "Anomalous Behaviour of Synchronizer and Arbiter Circuits", IEEE Transactions on Computers, April 1973, pp. 421-2; and G. R. Couranz, et al., "Theoretical and Experimental Behaviour of Synchronizers Operating in the Metastable Region", IEEE Transactions on Computers, Vol. C-24, No. 6, June 1975. Both of these articles suggest that the problem be solved by appropriately increasing the wait time before using the output of the synchronizing flip-flop.